FIG. 1 illustrates one type of prior art current mode DC/DC switching power supply, also known as a current mode DC/DC converter. Many other converter configurations can also benefit from the present invention. The type of converter shown in FIG. 1 is a peak current mode converter.
The operation of the converter is conventional and is as follows.
A clock (Clk) signal is applied to the set input of an RS flip flop 20.
The setting of the RS flip flop 20 generates a high signal at its Q output. A logic circuit 24, in response, turns the transistor power switch 26 on and turns the synchronous rectifier switch 28 off. Both switches may be MOSFETs or other transistors. A diode may replace the synchronous rectifier switch 28. The logic circuit 24 ensures that there is no cross-conduction of switches 26 and 28. The input voltage Vin applied to an inductor L1 through the switch 26 causes a ramping current to flow through the inductor L1, and this current flows through a low value sense resistor 32. The ramping current is filtered by an output capacitor 36 and supplies current to the load 38. The output capacitor 36 is relatively large to smooth out ripple.
The output voltage Vo is applied to a voltage divider 42, and the divided voltage is applied to the negative input of a transconductance error amplifier 44. Capacitors may be connected across the resistors in the divider 42 to further compensate the feedback voltage. A reference voltage Vref is applied to the positive input of the amplifier 44. The output current of the amplifier 44 corresponds to the difference between the actual output voltage Vo and the desired output voltage. The voltage (a control voltage Vc) across a capacitor 46 at the output of the amplifier 44 is adjusted up or down based on the positive or negative current output of the amplifier 44. The control voltage Vc at the capacitor 46, among other things, sets the duty cycle of the switch 26, and the level of the control voltage Vc is that needed to equalize the inputs into the amplifier 44. A resistor and capacitor may be connected in parallel with the capacitor 46 for controlling and optimizing the phase and loop stability, as is well known.
The control voltage Vc is applied to a pulse width modulation (PWM) comparator 50. The ramping voltage across the sense resistor 32, when the switch 26 is on, is sensed by a differential amplifier 52, having a certain gain, and, when the output of the amplifier 52 exceeds the control voltage Vc, the PWM comparator 50 is triggered to output a reset signal to the RS flip flop 20. This turns the switch 26 off and turns the synchronous rectifier switch 28 on to discharge the inductor L1, causing a downward ramping current. In this way, the peak current through the inductor L1 for each cycle is regulated to generate a desired output voltage Vo. The current through the sense resistor 32 includes a DC component (the lower frequency, average current) and an AC component (the higher frequency, ripple current).
FIG. 1 also illustrates a conventional slope compensation circuit 59, as is well known for current mode power converters. At high duty cycles (typically greater than 50%), the slope compensation circuit 59 turns off the switch 26 before the inductor current ramp crosses the control voltage Vc to reduce sub-harmonic oscillations that may occur in the current loop at the high duty cycles. The effect of the slope compensation circuit 59 is unrelated to the present invention.
As will be described with respect to FIG. 3, switching noise (e.g., high frequency spikes and ringing) by the turning on and off of the switch 26 is coupled to the current sense circuit and causes false triggering of the PWM comparator 50, resulting in jitter and an increase of ripple on the output voltage Vo.
The voltage drop and the power dissipation across the low value sense resistor 32 become more and more significant with higher currents and lower output voltages. It is desirable to use a small value sense resistor to reduce its power dissipation. Unfortunately, providing a very low value sense resistor 32 results in a low signal to noise ratio of the sensing signal, causing imprecise switching, in addition to the switching noise problem. Furthermore, it is desirable to even eliminate the sense resistor altogether to save power loss and improve the converter efficiency.
Instead of detecting the inductor current through a sense resistor, the current through the inductor L1 may be sensed by detecting the voltage drop across the switch 26 (e.g., a MOSFET). The on-resistance of such a MOSFETs may be a few mohms. However, such sensing still results in a low signal to noise ratio of the sensing signal and imprecise switching, in addition to the switching noise problem.
FIG. 2 illustrates using the inherent DC winding resistance (DCR) of the inductor L1 to detect the inductor current. An inductor winding may have a DC resistance on the order of a few mohms. An RC network, comprising the series connection of a resistor R and capacitor C, connected across the inductor L1 is selected to have substantially the same time constant as that of the inductor and DCR so that RC=L1/DCR. Accordingly, the ramping voltage across the capacitor C will track the ramping current through the inductor L1. The voltage across the capacitor C is then sensed by the differential amplifier 52, and the remainder of the operation is the same as that described with respect to FIG. 1. The sensed voltage across the capacitor C includes a DC component (corresponding to the lower frequency, average current) and an AC component (corresponding to higher frequency, ripple current). In an application with a very low inductor DCR value, the converter of FIG. 2 suffers from the same switching noise problem and signal to noise ratio problem as described with respect to FIG. 1. Since the RC time constant must match the L1/DCR time constant for proper operation, the signal to noise ratio cannot be improved using the technique of FIG. 2.
FIG. 3 illustrates the problem with switching noise. The clock pulse 62 (Clk in FIGS. 1 and 2) turns on the switch 26 and turns off the switch 28. The switching causes a high frequency oscillation due to the various parasitic capacitances and inductances in the system. When the sensed inductor current signal rises to cross the control voltage Vc, triggering the PWM comparator 50, the switch 26 is turned off, creating switching noise. The resulting spike and oscillation can cause false triggering of the comparator 50, resulting in a jittering of the comparator 50 output. This jitter is shown by the variability 63 in the on-time 64 of the switch 26. This adversely affects the duty cycle control precision and the regulation of the output voltage Vo. The problem can become much worse in a multi-phase paralleled converter in which switching noises can be coupled among phases.
What is needed is a current sensing technique for a switching power supply that reduces the jitter stemming from switching noise and also improves the signal to noise ratio of the current sense feedback loop.